Voltage-comparative-type comparators frequently used for a control circuit and the like generally include two MOS transistors of which the gates receive one of differential input signals, two current routes of which the currents are controlled by the MOS transistors thereof according to the voltage of the differential input signal, and a latch unit configured to amplify and hold potential difference between the current routes.
Accordingly, in the event of executing comparison between the voltages of the differential input signals with the above comparator according to the difference of properties of the above MOS transistors, or the amplification and holding property of the latch unit, error occurs. As a result thereof, conversion error occurs in an analog-to-digital converter configured of this voltage-comparative-type comparator.
Related art is discussed in P. M. Figueiredo, P. Cardoso, A. Lopes, C. Fachada, N. Hamanishi, K. Tanabe, and J. Vital, “A 90 nm CMOS 1.2V 6 b 1 GS/s Two-Step Subranging ADC,” IEEE International Solid-State Circuits Conference, Session 31/31.2, February 2006, and J. Craninckx and G. Van der Plas, “A 65 fJ/Conversion-Step 0-to-50 MS/s 0-to-0.7 mW 9 b Charge-Sharing SAR ADC in 90 nm Digital CMOS,” IEEE International Solid-State Circuits Conference, Session 13/13.5, vol. XL, pp. 246-247, 600, February 2007.